1. Field of the Invention
The present invention relates to an electronic circuit testing apparatus that is preferable for testing an electronic circuit that carries out, by inductive coupling, communications between substrates such as IC (Integrated Circuit) bare chips, and PCBs (Printed Circuit Boards).
2. Description of the Related Arts
The present inventor et al. have proposed realizing a system in package (SiP) that is capable of sealing a plurality of bare chips in one package of LSI (Large Scale Integration) by utilizing a method for three-dimensionally mounting chips and electrically connecting between chips by means of inductive coupling (Patent Document 1).
FIG. 3 is a view depicting a configuration of an electronic circuit according to the invention of Japanese earlier application. The electronic circuit is composed of the first through the third LSI chips 31a, 31b and 31c, which is an example in which LSI chips are stacked up in three layers and a bus is formed so as to lie across three chips. That is, it composes a single communications channel capable of carrying out communications between the three (between three LSI chips). The first through the third LSI chips 31a, 31b and 31c are vertically stacked up, and the respective chips are fixed to each other with an adhesive agent. The first through the third transmitter coils 33a, 33b and 33c, which are respectively used for transmission, are formed by wiring on the first through the third LSI chips 31a, 31b and 31c, and also the first through the third receiver coils 35a, 35 band 35c, which are respectively used for receiving, are formed by wiring thereon. These coils are disposed on the first through the third LSI chips 31a, 31b and 31c so that the centers of the openings of the three pairs of transmitter and receiver coils 33 and 35 are made coincident with each other. Accordingly, the three pairs of transmitter and receiver coils 33 and 35 form inductive coupling, thereby enabling communications. The first through the third transmitter circuits 32a, 32b and 32c are connected to the first through the third transmitter coils 33a, 33b and 33c respectively, and the first through the third receiver circuits 34a, 34b and 34c are connected to the first through the third receiver coils 35a, 35b and 35c respectively. The transmitter and receiver coils 33 and 35 are three-dimensionally mounted as coils having one or more turns in an area permitted for communications, utilizing a multilayer wiring of a process technology. A profile best suitable for communications exists in the transmitter and receiver coils 33 and 35, and it is necessary that they have an optimal number of times of winding, optimal opening and optimal line width. Generally, the transmitter coils 33 are smaller than the receiver coils 35.    [Patent Document 1] Japanese Patent Application No.